library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;


entity CLAgenerator is
port(  P 	  : in std_logic_vector(3 downto 0);
		 G 	  : in std_logic_vector(3 downto 0);
		 C_zero : in std_logic;
		 C 	  : out std_logic_vector (4 downto 0)
);
end CLAgenerator;

architecture Behavioral of CLAgenerator is
begin
       C(0) <= C_zero;
       C(1) <= G(0) or (C_zero and P(0));
       C(2) <= G(1) or (G(0) and P(1)) or (C_zero and P(1) and P(0));
       C(3) <= G(2) or (G(1) and P(2)) or (G(0) and P(2) and P(1)) or (C_zero and P(2) and P(1) and P(0));
       C(4) <= G(3) or (G(2) and P(3)) or (G(1) and P(3) and P(2)) or (G(0) and P(3) and P(2) and P(1)) or (C_zero and P(3) and P(2) and P(1) and P(0));
end Behavioral;

